前苏联专利SU1277910A3 Device for display and storage of television picture

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专利摘要:
An apparatus for the display and storage of television picture information by using a memory accessible from a computer in which the memory comprises dynamic RAM memory elements arranged in memory blocks being accessed in repetitive cycles. The address inputs of the memory elements are controlled by an address generator through an address modifying circuit and an address switching unit. The address modifying circuit modifies the picture addresses provided by the address generator corresponding to the internal address requirements of the memory blocks. The address switching unit is connected both to predetermined address lines of the address generator and to address lines of an interface providing connection towards the computer. The data bus of the memory is coupled to a data switching unit having outputs coupled to a parallel to series converter and to the multiplexer of the interface. The control of the data and address switching units is carried out by the least significant horizontal address bits. Owing to the specific kind of control a part of the memory blocks is always connected to the computer and an other part to the display unit, and these connections are cyclically interchanged. This control provides for the continuous refreshment of the dynamic RAM memories, and the apparatus will be in a quasi-continuous connection both with the display and the computer.
公开号:SU1277910A3
申请号:SU813370150
申请日:1981-12-25
公开日:1986-12-15
发明作者:Сенеш Жужа；Эндреди Бела
申请人:Самиташтехникай Координациош Интезет (Инопредприятие)；
IPC主号:

专利说明:

The invention relates to devices for displaying and storing information of a television image (frame), using memory devices accessed by a computer. The aim of the invention is to increase the speed due to the fact that the time of the computer is significantly shorter than the length of the television line, whereby a high speed of information flow to and from the computer, i.e. the duration of the full description of the image (frame) becomes shorter. I FIG. 1 is a schematic representation of a monitor screen (cathode ray tube) with horizontal and vertical decomposition; in fig. 2 - the same, with the four most significant address bits; in fig. 3 - memory, necessary for describing the visible area of the image (frame); in fig. 4, the transformation of the storage areas in FIG. 5 is a block diagram of the device; in fig. 6 is a block diagram of the address modification block; in fig. 7 is a diagram of a device with an embodiment of a memory block. The device (FIG. 5) contains a central clock generator 1, a synchronization unit 2, an address generator 3, an interface unit 4, an address switch 5, a multiplexer 6, an address modification unit 7, block 8 memory, memory management unit 9, information switch 10, shift register 11, digital-to-analog converters 12 and 13, address bus 14, control switch 15 input address, information bus 16, multiplexer input 17 6. Block 7 contains a multiplexer 18. On FIG. Figure 1 shows the visible image area of the television monitor screen (cathode ray tube). This useful display area must be compared with the associated memory. If there is a need to preserve the standard 4: 3 aspect ratio with almost identical horizontal and vertical decomposition, then the corresponding memory cells should be compared with each visible raster line, i.e. vertical decomposition should be equal to some raster line. During the return stroke when changing the frame, the lines are not visible, therefore, the number of visible raster lines turns out to be less than the total number of raster lines in any image. If a standard image of 625 lines is used, then the image utilization efficiency is sufficiently high when the memory capacity corresponds to 576 horizontal lines. If a fixed 4: 3 ratio between vertical and horizontal image sizes is taken, the horizontal decomposition is 768 vertical columns that can be displayed on the screen. Indeed, when choosing this number, the ratio of 4: 3 is observed, since the number of raster points in the row is 768 12 X 64, and in the column is 576 9 X 64. If such detailed decomposition is not required, then without significant changes to the system design, you can achieve twice larger decomposition in both directions with four times less memory capacity, in which the number of raster points in a row is 384 12x32, and in a column it is 288 9 x 32. As shown in FIG. 1, 768 horizontal distinguishable states can be defined by ten binary addresses, and an additional ten BINARY; addresses are needed to determine 576 distinguishable states vertically. Nine addresses are not enough to determine all states vertically, because nine binary addresses can determine a maximum of 2,512 states, which is less than the required number 576. The Kazkda elementary point of a television monitor that has a memory is determined, therefore, by the values of ten addresses horizontally and ten addresses vertically. Suppose that Xjj, X p ... .Xg and Xd denote horizontal addresses, 1, W., ..., Y0 and Yq - vertical addresses correspond to 1X elementary raster points, among which the least significant addresses are X and Y, and most of all; they are X and Y. FIG. Figure 2 shows the visible area of the image, divided in horizontal direction by 12 and in the vertical direction into 9 element areas. Each of these elementary regions has a rectangular shape and contains 64 raster points in each of two directions, for a total of 64 points. From the assumption of a binary address system, it follows that within each of these elementary areas the corresponding raster points are determined by the least significant scatter of address bits along the horizontal and vertical lines, i.e. addresses X,; ,, ..., Xj horizontally and addresses PP, U,, ..., U. vertically . The selection of one required of these elementary areas is provided by specifying the most significant address bits. FIG. 2, along the top and left edges, the numerical values of the addresses of the elementary regions are affixed and are associated with the binary values of the corresponding significant addresses X, X, Xg, and Y, horizon, ali, and Y, U, Uz, and U addresses, along the hyperthick. If these binary addresses are read as binary numbers, the values of these numbers are the coordinates of the corresponding elementary regions. FIG. 3 is similar to FIG. Figure 2 shows the elementary regions, each of which contains a 64x64 dot caliper, the numerical values of the elementary regions are also stamped along the top and left edges of the full area. The numbers that are vertical addresses are preceded by the binary values of the associated most significant bit of the address WO by the vertical. I Since known memory devices have an integer number of address inputs, the use of a memory area that describes the image area with a 4: 3 ratio is inefficient. If the addressing elementary areas (each of which contains 64 points) is performed assuming that the area is a single object, then for each direction four address bits are required, and from the corresponding storage capacity defined by 16x16 such single areas, only 9x12 areas contain useful information. FIG. 3, a dashed line marks half of the entire storage capacity, which can be vertically addressed by three bites instead of the required chats. FIG. 4, such a memory region allows the addressing to be rotated by means of three bits and horizontally by means of four bits. Such a memory may be implemented by storage devices, the capacity of which is half as compared with that required for describing the area shown in FIG. 3. The three vertical bits mentioned above actually illustrate the use of the vertical address of the binary address, since the full address additionally contains the six least significant address bits that are needed to determine the address within the corresponding elementary regions. If we compare fig. 3 and 4, it can be seen that the bottom line of the elementary areas (i.e., the last 64 lines of the visible image) is omitted in FIG. 4. This last line of areas can be broken down into three fields: A, B, and C, each of which is associated with an actual image information number 1 that needs to be described in memory. FIG. 4, it can be seen that the floors A, B and C can be placed in the first three lines of the last four horizontal areas. The horizontal address with its four bits can define sixteen horizontal regions, of which only twelve are required for the actual existing elementary regions. The remaining last empty cells of the memory can be used to describe the fields A, B, and C. As can be seen from FIG. 4, with this distribution, the last four cells from the last five lines of the memory remain empty. It is possible to establish the correspondence by means of the modified addresses between the surface area (Fig. 2) and the actual storage capacity (Fig. 4). The addressing of elementary raster points is performed in ten horizontal and ten vertical ranges, i.e. A total of twenty addresses, and these addresses determine the corresponding raster points when the device is under the control of a computer. This way of addressing the question is impudent, i.e. addresses) can be easily traced, and the programs built on such addresses are simply checked. 12 Actual memory addressing, however, occurs only after modifying the above-mentioned address addresses, also called image addresses, the image address modification is performed by the address modification block (fcg , 6), which contains a multiplexer, has 1 eight inputs and four outputs, as well as a selection control input SEL, a control of the Y bit, vertical addresses. The eight inputs receive the Xg and Xq bits of the horizontal address and the Y, Y-, and Ud bits of the address vertically. From the four outputs, bits x and Xg of the modified address are removed horizontally and the bits Y and Y, the modified address. Vertically. The purpose of the address modification block is to translate the elementary fields A, B, and C into the memory fields shown in FIG. 4. When comparing FIG. 3 and 4, it can be seen that when the Ud bit of the address in the vertical is zero (0), the image (frame) is scanned in the top eight lines of the regions and there is no need to modify the addresses. When the value of the Y bit, the vertical address becomes 1, then. modification is required. As can be seen in FIG. 4, in the last four areas with horizontal addresses (on the right) of this memory, the most significant bits X and Xg of addresses horizontally have a value of 1. If during address modification in the Ud case, the value of the Xg and X addresses changes by 1, then, the formed addresses determine the last four regions horizontally of this memory, when the electron beam scans the fields A, B., and C along the ninth row of regions. It is characteristic of field A that, in the course of its existence, the values of the Xg and Xq bits of the addresses are equally equal to O. From this. . It follows that the above-mentioned modification of the address address horizontally converts the field A to the field A (Fig. 4). Bit Oud does not participate in the formation of the address of this memory. During the scanning of the field B, special measures should be taken so that the modified addresses determine the field B shown in FIG. 4. In FIG. 3, it can be seen that for the field in bit XD 0, the horizontal address is 1. In FIG. 4 modified, the field B has an address vertically, in which Y 1. The address modification block 7 satisfies this condition, ensuring the equality X „Y, if I 1-. Similarly, when the electron beam scans the C field, the modified address must determine the C field. For field C, it is true that Xg 1 (Fig 3). In field c, condition Y 1 must be satisfied. Block 7 ensures that this condition is met. . . The address modification block 7 alters the least significant six horizontal and vertical addresses X,, ... X5 and Y (,,,,, by means of which memory cells associated with the corresponding raster points are defined inside the corresponding elementary areas. The address modification is not affected addresses b t and Xg. Modified addresses are summarized in the table UE 1 If the address modification block is used, the most significant bit Va of the address in the vertical is not transmitted for further use, since the main role of this address bi It consists of properly managing the address modification process. This explains why only nineteen bit addresses should be
associated with the address inputs of the actual memory when the total number of image addresses is 20. When using twenty image addresses, operation and programming remain easy to perform and visual control, while modifying the addresses saves half of the required storage capacity.
The central clock generator 1 (Fig. 5) generates clock pulses with a frequency of about 15 kHz, the address generator 3 in response to clock pulses generates addresses horizontally and vertically necessary for addressing the memory. Address bus 14 contains the address lines through which addresses X ,, ..., Xa horizontally and the addresses Y, ..., Od vertically are transmitted. The synchronization unit 2 generates synchronization pulses for a television monitor, which are phase bound to the image addresses and mixed with the output video signals generated by the device in order to create a standard composite video sequence. one. .
Switch 5 address consists of a small number (one of two) multiplexers. The output of the address switch 5, depending on the logical value of the control signal arriving at its control input 15, forms the logical values of the signals controlling either the first or the second group of inputs. The second inputs of the switch 5 address are connected: With an external computer or terminal (not shown). The display monitor and the computer alternately gain access to the memory unit 8 of the device. The addressing mode of memory block 8 is similar for both of these cases. The addresses of the displayed raster points are always determined by the state of the address bus 14 of the address generator 3. Memory access initiated by an external computer is determined by the address sent from the computer through the interface 4. In order to distinguish the addresses coming from the computer and the normal addresses of the image, the computer addresses horizontally and vertically are designated AX, AX, ... AX, and AU, AU,. .., AU,,
A computer has access to memory only in certain working phases.
which are performed by the input connection. Access is permitted at the address of the interface 4 block with one of the address lines, for example with the Hd line of addresses 5 horizontally of the address generator 3.
The memory management unit 9 sets the memory unit 8 with the proper operation modes (write mode or read mode 0). In the operating mode, when communication is established between the information switch 10 and the television monitor, the switch 10 is connected directly to the intermediate memory, which can be implemented in the preferred embodiment in the form of a shift register 11 controlled by the least significant addresses (XQ, X , X and Xj) horizontally and 0 performing the conversion of a parallel code into a sequential one. The serial output of the shift register 11 is connected to a digital-to-analog converter 13, which supplies analog values read out in the form of analog voltages to its analog output.
The device makes it easy to read external video signals from memory block 8. In this case, suitable circuits (not shown) ensure that the video signals to be recorded arrive synchronously with the addresses horizontally and vertically of this device. For analog signals input to the video signal, analogue. digital converter 12 generates digital signals input to the serial input of shift register 11, 0 The recording mode is set by the computer through interface 4 and block 9, In this case, the information entering in serial form into shift register 11 can be recorded through the information switch 10, in parallel form to the memory block 8, receiving the signal. Recording is allowed.
0 Throughout the time periods of a friend’s computer, the output group of information switch 10 operates as a continuation of the information bus 16. This output group consists of a set of parallel bit lines connected to the inputs of a multiplexer 6. The latter has a status control input 16 and a logic state The latter is determined by the selection of the input that is connected to the information line of the interface 4. The above-mentioned connection between the information line and the information bus 16 is intended to ensure bidirectional information transfer, so that the computer is able to write and read from memory block 8. The proposed device can memorize six bits of information at each address. This means that the memory is composed of six memory elements controlled in parallel, and these elements connected to the information bus 16 can transmit signals corresponding to output information of length p six bits. According to the six-bit information unit, the digital-to-analog converter 13 can provide 2 64 gradation steps or, if a color display is used, 64 different colors on the monitor screen. In the latter case, the standard RGB signal must be formed from the output signal of the digital-to-analog converter 13, the device operates as follows; If the conditions described by Bbmie (Figs. 1-4) are met, 768 raster dots can be displayed during each scan of a television raster line (if an increased degree of decomposition is used). As for the visible part of the raster line, the duration of each rast. the flat point is about 66 ns. The period of the clock impulses generated by the central clock generator 1 is about 66 n, and according to these clock pulses, the address generator 3 forms the addresses vertically and horizontally. Horizontal addresses are formed by appropriately dividing clock pulses into successive powers of 2, and the length of the horizontal address period Xd is equal to the duration of clock pulses. In dynamic memories with an arbitrary order of access, the storage elements are capacitors. Losses in these condensate Topopaxes need to be compensated for at least after each period of 2 ms. This operation is referred to as recovery (upgrade). If the update does not occur after a period of 2 ms, then the recorded information is lost. The addressing system is designed in such a way that the first half of the address bits are used by the signal Gating the row addresses denoted by RAS, and the second half is used by the signal Gating the column addresses designated the CAS. For the update, it is sufficient that the first half of the address bits are used either for writing or for reading at repeated intervals that are shorter than 2 ms. The number of address inputs to a dynamic memory with an arbitrary order of circulation is half the number of bits necessary for their full addressing. Full addressing occurs at two subsequent points. In the first step, together with the installation of the RAS signal, i.e. the first group of a mixture of address bits, and in the second step, together with the CAS signal, the second group of seven address bits should be connected to the address inputs. Signal Recording is allowed to be set together with the formation of a CAS signal. If the signal Write is not allowed, set the read mode. Following the address setting after a certain delay has elapsed, readable information is available, and in the write mode, information is entered (in the memory) after the corresponding delay has elapsed, which is counted after the address setting. - This delay is a significant part of the duration of the dynamic memory access and is usually 150-300 no. The cost of a dynamic memory increases with shortening the duration of the call. When using well-known integrated components, the unit cost of storage per unit of stored information is minimal if dynamic memory is used with storage capacitances of 16Kx1 bits, preferably 64Kx1 bits. The following describes the operation of the preferred embodiment of the device for the case when the memory 180 is composed of several dynamic memories with a storage capacitance of 16Kx1 bits addressed in parallel. 14 bits are required for addressing the memory with such a capacitance. At the output of the address generator 3, the addresses X, X, .. ,, X are formed horizontally and the addresses of the PP, U,, ..., Wo vertically (twenty addresses in total). Each address pattern is assigned to the elementary raster points in the visible image area. Out of the twenty input address lines, the address modification block 7 only skips over nineteen signals, since so many bit lines are enough to address a given number of 768x576 raster points. The dynamic memory elements forming the memory block 8 can be addressed by 14 bits. The long five address lines cannot be directly used to address this memory. If the B block of memory is made up of 2 32 storage elements and each has a cumulative capacity of 1bKx1 bits, then the remaining five bits should be used to select a given stopping element. The device is described below in which the reading from the memory for the display monitor takes place synchronously with the scanning of the electron beam, the storage elements are updated within the specified maximum periods of 2 ms and at the same time the computer has free access to all memory cells. . I FIG. 7 illustrates a device diagram with an embodiment of the memory block 8. Suppose there is only one bit stored in each raster point. If a larger amount of information is required. D; Must be stored in dp of corresponding raster points, it is necessary to increase the number of storage elements. The storage elements of memory block 8 are grouped into two blocks: B a and Bfc, each of which contains a pair of groups of storage elements, each group containing n eight elements. According to the scanning rule of alternating half-frames in television, it follows that two adjacent lines, which are located next to the visible image, are associated with separate half-frames, one after the other. The duration of each half frame is 20 ms. If this is compared with the vertical addresses shown in FIG. 1 and 2, it can be seen that the value O of the address Ud vertically defines the first half-frames, and the value 1 of this address determines the second half-frames. According to The corresponding storage blocks 8a and 8b have one group of eight storage elements associated with the value V0, and the other group with the value of SV 1. Block 9 is organized in such a way that, depending on the value, V-it uses one of these two groups. Inside the blocks, sixteen storage elements are connected in parallel. Since the address Y is used to select the desired group of storage elements, only four addresses remain to be allocated, since the corresponding storage elements can be addressed via fourteen bits. The difference between the corresponding blocks B and 8b is that block Ba stores information associated with raster points. having the address X 1 horizontally, while the second block B & stores information for points with horizontal Xd O addresses. From the point of view of addressing, the blocks Za and Bb can be considered addressable in parallel, although in fact the address switch 5 and the information switch 10 connect the corresponding blocks alternately to a television monitor or interface 4 connected to a computer. If Xj is 1, the address switch 5 connects the address generator 3 via block 7 q to the address lines of the upper block 8a. In this case, the eight storage elements are read out parallel to the block B q and the read information is written to the eight parallel cells of the shift register 11 via the information switch 10. At the same time, interfacing unit 4 assigns the addresses AX O to the computer and the address switch 5 opens the address lines going from block 4 through 13 12 block 7b to the memory elements of the lower block 8b. The information lines of the storage elements of the 8fe unit are switched by the information switch 10 with the multiplexer 6. When the value of X changes to O, the functional roles will necessarily change, i.e. the address and data lines of the upper block 8q must be commuted with block 4 and the lower block 8 in the memory must be commuted with the monitor. Consequently, these blocks are alternately switched either to a computer or to a monitor, depending on the state X, and during each of these connections there is a write or read operation that corresponds to sending information of 8 bits in length. Obviously, the sequential switching of the blocks described above may not be fulfilled if the individual blocks contain sixteen parallel memory elements, which differ in accordance with the value Y ,,. In such cases, however, the simultaneous execution and switching of sixteen bits is required, and creating and matching buses with a high number of bits is undesirable (taking into account the cost). For any value of the values shown in FIG. 3, matching groups of 8 bits in length are present at the parallel inputs of register shift 11. As a trace of the received addressing method, each period X consists of 8 full periods XQ. If shift register 11 is clocked by pulses of frequency ZX (with time periods of about 66 n) information recorded in parallel. into shift register 11, it is pushed into digital-to-analog converter 13 (Fig. 5) and the monitor receives updated information every 66 days. Instead of the shift register 11, a multiplexer with eight inputs and one output can be used if it is set to the addresses X, X, and Y, Of the four remaining address bits mentioned above, one choice is chosen to control the choice between blocks, for example X, and as before, the remaining three address bits are used to control the conversion from a parallel code to a serial one, 0 executed by the shift register 11 or a multiplexer. Since the blocks are alternately switched to the shift register 11, the corresponding blocks are accessible from the computer side in each half period X. Obviously, if the memory block 8 is selected with a larger storage capacity and more than 14 bits are allocated to determine the address in it, then the problem of memory allocation is much simpler since even fewer address bits must be used to convert parallel code to serial, i.e. the length of the shift register can be reduced. Another embodiment can be proposed for the case when the degree of decomposition is sufficiently reduced. With a doubly coarser decomposition in both directions (in comparison with the standard reference above), the device scheme (Fig. 7) can be modified so that there is no need to duplicate memory elements in memory blocks corresponding to Od values, since both half-frames contain identical information, as well as the frequency of the clock pulses, can be reduced to half the value that it has upon detailed decomposition. With such a modification, it is enough to send four bits in parallel instead of eight from and to the memory. With such a decomposition, the required amount of memory is therefore one quarter of the amount needed for a larger decomposition. Continuous updating of dynamic storage elements can be achieved by rational allocation of 14 memory addressing bits. Each address assigned together with the RAS signal should appear within repetitive intervals (periods that are shorter than 2 ms). Of the addresses, the addresses are horizontally. X ,, X ,, X ,, and X, ,, -1 ld are not used to directly address the storage elements. The remaining addresses change in each line, and due to the distribution of the modified addresses (4 and 6) in the lines associated with the Verify Od addresses, not every value of the X address in the vertical is used; In addition, the use of Xg addresses is impractical, since only these addresses can be used to perform an update that takes place in periods of less than 2 ms. The preferred distribution of actual memory addresses is presented below for storage elements with a capacity of 1bKx1 bits each. Memory addresses set together with RAS-signals, the following: X, X, X, X and Y, Y, Y. Out of these addresses, addresses on the horizon can take any combinatorial value in each television line, and the least significant address Od in the vertical appears, at least in every eighth television line, i.e. possesses a period of 512 µs. With the use of these addresses, the memory update requirement is well satisfied since the update is performed within a 2 ms interval. The memory addresses set with local CAS signals are as follows: Y and Y: Ag, Ld 4 S J.6 of the remaining addresses, In purpose, block 7.55 determines the validity of groups of blocks 8a and 8b (in accordance with the change of half-frames), XQ, X, and Xg are used to control the conversion of the parallel code to the sequence, X., initially used to control the choice between blocks memory and then for control The sequence of access to computer memory and display monitor. I Memory blocks 8o | And 8b can be divided into two parts with the control of groups of four memory elements in parallel. If the switching of addresses and information between groups is carried out by means of the address X, then the length of the code converted from parallel to serial can be reduced to two bits, i.e. The shift register can contain four cells. In this case, however, the memory cycle of the memory groups managed in accordance with the different values of the address Y must be shifted in time by one cycle in order to ensure a sufficient time interval between them for unhindered access to the computer. is that informational whether
Scientific research institutes carrying four bits can be used instead of eight-bit information lines (as in Figs. 5 and 7), which provides material cost savings.

权利要求:
Claims (1)
[1]
Apparatus of the Invention A device for displaying and storing television image information comprising a memory unit, a central clock generator, an address generator, a synchronization unit, a interface unit, a memory management unit, an address switch, an address modification unit, and an information switch, the output of the central clock generator is connected to the input of the address generator, the first output of which is connected to the input of the synchronization unit, address, the outputs of the output group of the interface block are connected to the first group of informs address inputs of the switch, the output of which is connected to the input of the address modification block, the output of which is connected to the address of the memory block, whose input / output is connected to the first information output output of the information switch, characterized in that, in order to improve speed , it contains a multiplexer, a shift register and two digital-to-analog converters, moreover, the second group of information inputs of the address switch is connected to the address outputs of the output group of the address generator and to the first input of the block interface, the second input and output of which are connected respectively to the output of the multiplexer and the first input of the memory control unit, the second input of which is connected to the second output of the address generator, the control outputs of the group of outputs of the address generator are connected to the control inputs of the address switch, information switch and the shift register, the clock input of which is connected to the first output of the memory control unit, the second output of which is connected to the control input of the memory block, the group of inputs of the multiplexer is connected with the group of outputs of the interface unit, and the information input-output of the multiplexer is connected with the second information output-input of the information commutator,, the information source input-output of the coordinator is connected with the first information
nym. Vkodom-input shift register, the output of which through the first digital-to-analog converter connected to the video output of the device, video input
which through the second digital-to-analog converter is connected to the second information input of the shift register.
(ABOUT)
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类似技术:

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同族专利:

公开号 | 公开日

EP0051655B1|1985-09-25|

WO1981003234A1|1981-11-12|

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HU180133B|1983-02-28|

EP0051655A4|1982-09-15|

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法律状态:

优先权:

申请号 | 申请日 | 专利标题

HU80801110A|HU180133B|1980-05-07|1980-05-07|Equipment for displaying and storing tv picture information by means of useiof a computer access memory|

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